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the information in this document is subject to change without notice. before using this document, please confirm that this is the latest version. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. 2002 mos integrated circuit pd160061 384-output tft-lcd source driver (compatible with 64-gray scales) data sheet document no. s15843ej3v0ds00 (3rd edition) date published june 2004 ns cp (k) printed in japan the mark shows major revised points. description the pd160061 is a source driver for tft-lcd?s capable of dealing with displays with 64-gray scales. data input is based on digital input configured as 6 bits by 6 dots (2 pixels), which can realize a full-color display of 260,000 colors by output of 64 values -corrected by an internal d/a converter and 5-by -2 external power modul es. because the output dynamic range is as large as v ss2 + 0.2 v to v dd2 ? 0.2 v, level inversion operation of the lcd?s common electrode is rendered unnecessary. also, to be able to deal with dot-line inversion, n-line inversion and column line inversion when mounted on a single side, this source driv er is equipped with a built-in 6-bit d/a converter circuit whose odd output pins and even output pins respectively output gray scale voltages of differing polar ity. assuring a maximum clock frequency of 65 mhz when driving at 2.7 v, this driver is applicable to xga-standard tf t-lcd panels and sxga tft-lcd panels. features ? cmos level input (2.3 to 3.6 v) ? 384 outputs ? input of 6 bits (gray-scale data) by 6 dots ? capable of outputting 64 values by means of 5-by-2 exte rnal power modules (10 units) and a d/a converter (r-dac) ? logic power supply voltage (v dd1 ): 2.3 to 3.6 v ? driver power supply voltage (v dd2 ): 7.5 to 9.5 v ? high-speed data transfer: f clk = 65 mhz max. (internal data transfer speed when operating at v dd1 = 2.7 v) 40 mhz max. (internal data tr ansfer speed when operating at v dd1 = 2.3 v) ? output dynamic range: v ss2 + 0.2 v to v dd2 ? 0.2 v ? apply for dot-line inversion, n-line inversion and column line inversion ? output voltage polarity inversion function (pol) ? input data inversion functi on (capable of controlling by eac h input port) (pol21, pol22) ? apply for heavy load, light load ? semi slim-chip shaped ordering information part number package pd160061n-xxx tcp (tab package) pd160061nl-xxx cof (cof package) remark the tcp?s/cof?s external shape are customized. to order the required shape, so pl ease contact one of our sales representatives.
data sheet s15843ej3v0ds 2 pd160061 1. block diagram 64-bit bidirectional shift register data register latch level shifter d/a converter voltage follower output d 00 d 05 sthr s 1 -------------------------------- sthl r,/l clk v dd1 v ss1 c 1 c 2 c 3 - - - - - - - - - - - - - - - - - - - - - - c 63 c 64 pol v 0 to v 9 v dd2 v ss2 s 2 s 3 s 384 stb d 10 d 15 d 20 d 25 pol21 to to to to to to d 30 d 35 d 40 d 45 d 50 d 55 pol22 src lpc hpc remark /xxx indicates active low signal. 2. relationship between ou tput circuit and d/a converter 6-bit d/a converter multi- plexer pol v 0 : v 4 v 5 : v 9 s 1 s 2 s 383 s 384 5 5
data sheet s15843ej3v0ds 3 pd160061 3. pin configuration (copper foil surface) ( pd160061n-xxx: tcp (tab package): face-up/ pd160061nl-xxx: cof (cof package): face-down) s 384 s 383 sthl s 382 d 55 s 381 d 54 d 53 d 52 d 51 d 50 d 45 d 44 d 43 d 42 d 41 d 40 d 35 d 34 d 33 d 32 d 31 d 30 v dd1 lpc r , /l v 9 v 8 v 7 v 6 v 5 v dd2 v ss2 v 4 v 3 v 2 v 1 v 0 hpc v ss1 src clk stb pol pol21 pol22 d 25 d 24 d 23 d 22 d 21 d 20 d 15 d 14 d 13 d 12 d 11 d 10 d 05 d 04 d 03 s 4 d 02 s 3 d 01 s 2 d 00 s 1 sthr ic pad surface remark this figure does not spec ify the tcp or cof package.
data sheet s15843ej3v0ds 4 pd160061 4. pin functions (1/2) pin symbol pin name i/o description s 1 to s 384 driver output output the d/a conver ted 64-gray-scale analog voltage is output. d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 d 40 to d 45 d 50 to d 55 display data input input the display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). d x0 : lsb, d x5 : msb r,/l shift direction control input these refer to the start pulse i/o pi ns when driver ics are connected in cascade. fetching of display data starts when h is read at the rising edge of clk. r,/l = h (right shift): sthr input, s 1 s 384 , sthl output r,/l = l (left shift): sthl input, s 384 s 1 , sthr output sthr right shift start pulse input/output i/o sthl left shift start pulse input/output these refer to the start pulse i/o pins when driver ics are connected in cascade. fetching of display data starts when h is read at the rising edge of clk. when right shift: sthr input, sthl output when left shift: sthl input, sthr output a high level should be input as the pulse of one cycle of the clock signal. if the start pulse input is more than 2clk, the first 1clk of the high-level input is valid. clk shift clock input input refers to the shift register?s sh ift clock input. the display data is incorporated into the data register at the rising edge. at the rising edge of the 64th after the start pulse input, the start pulse output reaches the high level, thus becomi ng the start pulse of the next-level driver. if 66th clock pulses are input after input of the start pulse, input of display data is halted automatically. the contents of the shift r egister are cleared at the stb?s rising edge. stb latch input input the contents of the data register are tr ansferred to the latch circuit at the rising edge. and, at the falling edge of the stb, the gray scale volt age is supplied to the driver. when stb = h period, driver output level is hi-z (high impedance). it is necessary to ensure input of one pulse per horizontal period. pol polarity input input pol = l: the s 2n?1 output uses v 0 to v 4 as the reference supply. the s 2n output uses v 5 to v 9 as the reference supply. pol = h: the s 2n?1 output uses v 5 to v 9 as the reference supply. the s 2n output uses v 0 to v 4 as the reference supply. s 2n-1 indicates the odd output, and s 2n indicates the even output. input of the pol signal is allowed the setup time (t pol - stb ) with respect to stb?s rising edge. pol21, pol22 data inversion input input data inversi on can invert when display data is loaded. pol21: d 00 to d 05 , d 10 to d 15 , d 20 to d 25 , data inversion can invert display data pol22: d 30 to d 35 , d 40 to d 45 , d 50 to d 55 , data inversion can invert display data pol21, pol22 = h: data inversion loads display data after inverting it. pol21, pol22 = l: data inversion does not invert input data. lpc, hpc bias current control input input please refer to panel loads and driver power supply voltage (v dd2 ), when set up these pins. refer to 10. bias current control by lpc and hpc . lpc pin is pulled down to the v ss1 inside the ic, hpc pin is pulled up to the v dd1 inside the ic.
data sheet s15843ej3v0ds 5 pd160061 (2/2) pin symbol pin name i/o description src high driving time control input this pin is set up to high drive time of the output amplifier. please decide the pin setting refer to panel loads and one horizontal period. src pin is pulled up to the v dd1 inside the ic. src = h or open: high drive time 64 clk (normally period mode) src = l: high drive time 128 clk (long time mode) refer to 9. src and high drive time. v 0 to v 9 -corrected power supplies ? input the -corrected power supplies from outside by using operational amplifier. make sure to maintain the following relationships. during the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. v dd2 ? 0.2 v v 0 > v 1 > v 2 > v 3 > v 4 0.5 v dd2 v dd2 ? 0.3 v > v 5 > v 6 > v 7 > v 8 > v 9 v ss2 + 0.2 v v dd1 logic power supply ? 2.3 to 3.6 v v dd2 driver power supply ? 7.5 to 9.5 v v ss1 logic ground ? grounding v ss2 driver ground ? grounding cautions 1. the power start sequence must be v dd1 , logic input, and v dd2 & v 0 to v 9 in that order. reverse this sequence to shut down. 2. to stabilize the supply voltage, please be sure to insert a 0.1 f bypass capacitor between v dd1 to v ss1 and v dd2 to v ss2 . furthermore, for increased precision of the d/a converter, insertion of a bypass capacitor of about 0.01 f is also recommended between the -corrected power supply terminals (v 0 , v 1 , v 2 ,....., v 9 ) and v ss .
data sheet s15843ej3v0ds 6 pd160061 5. relationship between inpu t data and output voltage value the pd160061 incorporates a 6-bit d/a conver ter whose odd output pins and even output pins output respectively gray scale voltages of differing polarity with respect to the lcd?s counter electrode voltage. t he d/a converter consists of ladder resistors and switches. the ladder resistors (r0 to r62) ar e designed so that the ratio of lcd panel -compensated voltages to v 0 ? to v 63 ? and v 0 ? to v 63 ? is almost equivalent, resistor ratio is shown in figure 5 ? 2. for the 2 sets of five -compensated power supplies, v 0 to v 4 and v 5 to v 9 , respectively, input gray scale voltages of the same polarity with respect to the common voltage. when fine-gray scale voltage precision is not necessary, there is no need to connec t a voltage follower circuit to the - compensated power supplies v 1 to v 3 and v 6 to v 8 . figure 5?1 shows the relationship between the driving voltages such as liquid-crystal driving voltages v dd2 and v ss2 , common electrode potential v com , and -corrected voltages v 0 to v 9 and the input data. be su re to maintain the voltage relationships of below. v dd2 ? 0.2 v v 0 > v 1 > v 2 > v 3 > v 4 0.5 v dd2 0.5 v dd2 ? 0.3 v v 5 > v 6 > v 7 > v 8 > v 9 > v ss2 + 0.2 v figures 5?2 indicates ? -corrected voltages and ladder resistors ratio. fi gures 5?3 indicates the relationship between the input data and out put voltage. figure 5?1. relationship between input data and -corrected power supplies 0.2 v 0.2 v 00 10 20 3f input data (hex.) 16 v 0 30 v 1 v 2 v 3 v 4 v 6 v 7 v 8 v 9 16 16 15 0.3 v v 5 0.5 v dd2 split interval v dd2 v ss2 15 16 16 16
data sheet s15843ej3v0ds 7 pd160061 figure 5?2. -corrected voltages and ladder resistors ratio cautions 1. there is no connection between v 4 and v 5 terminal in the ic. 2. the resistance ratio is a relative ratio in the case of setting the resistance minimum value to 1. v 0 v 17 ?? v 16 ?? v 15 ?? v 1 ?? v 2 ?? v 0 ?? v 61 ?? v 60 ?? v 49 ?? v 48 ?? v 47 ?? r 60 r 59 r 49 r 48 r 47 r 46 v 6 r 61 r 17 r 16 r 15 r 14 v 8 v 62 ?? r 62 v 9 v 63 ?? v 5 v 47 ? v 48 ? v 49 ? v 61 ? v 62 ? v 63 ? v 2 ? v 3 ? v 15 ? v 16 ? v 17 ? r 2 r 3 r 14 r 15 r 16 r 17 v 1 r 1 r 46 r 47 r 48 r 49 r 60 r 61 r 62 v 3 v 4 v 1 ? r 0 r 2 r 1 r 0 v 0 ? rn ratio value (typ.) r0 8.5 800 r1 7.5 750 r2 7.0 700 r3 6.5 650 r4 6.0 600 r5 5.5 550 r6 5.5 550 r7 5.0 500 r8 5.0 500 r9 4.0 400 r10 4.0 400 r11 3.5 350 r12 3.5 350 r13 3.5 350 r14 3.0 300 r15 3.0 300 r16 3.0 300 r17 2.5 250 r18 2.5 250 r19 2.5 250 r20 2.0 200 r21 2.0 200 r22 2.0 200 r23 1.5 150 r24 1.5 150 r25 1.5 150 r26 1.5 150 r27 1.0 100 r28 1.0 100 r29 1.0 100 r30 1.0 100 r31 1.0 100 r32 1.0 100 r33 1.0 100 r34 1.0 100 r35 1.0 100 r36 1.0 100 r37 1.0 100 r38 1.0 100 r39 1.0 100 r40 1.0 100 r41 1.0 100 r42 1.0 100 r43 1.0 100 r44 1.0 100 r45 1.0 100 r46 1.0 100 r47 1.0 100 r48 1.0 100 r49 1.0 100 r50 1.0 100 r51 1.0 100 r52 1.0 100 r53 1.5 150 r54 1.5 150 r55 1.5 150 r56 2.0 200 r57 2.0 200 r58 2.5 250 r59 2.5 250 r60 3.0 300 r61 5.0 500 r62 8.0 800
data sheet s15843ej3v0ds 8 pd160061 figure 5?3. relationship between input data and output voltage (pol21, pol22 = l) output voltage 1: v dd2 ? 0.2 v v 0 > v 1 > v 2 > v 3 > v 4 0.5 v dd2 output voltage 2: 0.5 v dd2 ? 0.3 v v 5 > v 6 > v 7 > v 8 > v 9 v ss2 + 0.2 v input data 00h v 0' v 0 v 0'' v 9 01h v 1' v 1 +(v 0 -v 1 ) 7250 / 8050 v 1'' v 9 +(v 8 -v 9 ) 800 / 8050 02h v 2' v 1 +(v 0 -v 1 ) 6500 / 8050 v 2'' v 9 +(v 8 -v 9 ) 1550 / 8050 03h v 3' v 1 +(v 0 -v 1 ) 5800 / 8050 v 3'' v 9 +(v 8 -v 9 ) 2250 / 8050 04h v 4' v 1 +(v 0 -v 1 ) 5150 / 8050 v 4'' v 9 +(v 8 -v 9 ) 2900 / 8050 05h v 5' v 1 +(v 0 -v 1 ) 4550 / 8050 v 5'' v 9 +(v 8 -v 9 ) 3500 / 8050 06h v 6' v 1 +(v 0 -v 1 ) 4000 / 8050 v 6'' v 9 +(v 8 -v 9 ) 4050 / 8050 07h v 7' v 1 +(v 0 -v 1 ) 3450 / 8050 v 7'' v 9 +(v 8 -v 9 ) 4600 / 8050 08h v 8' v 1 +(v 0 -v 1 ) 2950 / 8050 v 8'' v 9 +(v 8 -v 9 ) 5100 / 8050 09h v 9' v 1 +(v 0 -v 1 ) 2450 / 8050 v 9'' v 9 +(v 8 -v 9 ) 5600 / 8050 0ah v 10' v 1 +(v 0 -v 1 ) 2050 / 8050 v 10'' v 9 +(v 8 -v 9 ) 6000 / 8050 0bh v 11' v 1 +(v 0 -v 1 ) 1650 / 8050 v 11'' v 9 +(v 8 -v 9 ) 6400 / 8050 0ch v 12' v 1 +(v 0 -v 1 ) 1300 / 8050 v 12'' v 9 +(v 8 -v 9 ) 6750 / 8050 0dh v 13' v 1 +(v 0 -v 1 ) 950 / 8050 v 13'' v 9 +(v 8 -v 9 ) 7100 / 8050 0eh v 14' v 1 +(v 0 -v 1 ) 600 / 8050 v 14'' v 9 +(v 8 -v 9 ) 7450 / 8050 0fh v 15' v 1 +(v 0 -v 1 ) 300 / 8050 v 15'' v 9 +(v 8 -v 9 ) 7750 / 8050 10h v 16' v 1 v 16'' v 8 11h v 17' v 2 +(v 1 -v 2 ) 2450 / 2750 v 17'' v 8 +(v 7 -v 8 ) 300 / 2750 12h v 18' v 2 +(v 1 -v 2 ) 2200 / 2750 v 18'' v 8 +(v 7 -v 8 ) 550 / 2750 13h v 19' v 2 +(v 1 -v 2 ) 1950 / 2750 v 19'' v 8 +(v 7 -v 8 ) 800 / 2750 14h v 20' v 2 +(v 1 -v 2 ) 1700 / 2750 v 20'' v 8 +(v 7 -v 8 ) 1050 / 2750 15h v 21' v 2 +(v 1 -v 2 ) 1500 / 2750 v 21'' v 8 +(v 7 -v 8 ) 1250 / 2750 16h v 22' v 2 +(v 1 -v 2 ) 1300 / 2750 v 22'' v 8 +(v 7 -v 8 ) 1450 / 2750 17h v 23' v 2 +(v 1 -v 2 ) 1100 / 2750 v 23'' v 8 +(v 7 -v 8 ) 1650 / 2750 18h v 24' v 2 +(v 1 -v 2 ) 950 / 2750 v 24'' v 8 +(v 7 -v 8 ) 1800 / 2750 19h v 25' v 2 +(v 1 -v 2 ) 800 / 2750 v 25'' v 8 +(v 7 -v 8 ) 1950 / 2750 1ah v 26' v 2 +(v 1 -v 2 ) 650 / 2750 v 26'' v 8 +(v 7 -v 8 ) 2100 / 2750 1bh v 27' v 2 +(v 1 -v 2 ) 500 / 2750 v 27'' v 8 +(v 7 -v 8 ) 2250 / 2750 1ch v 28' v 2 +(v 1 -v 2 ) 400 / 2750 v 28'' v 8 +(v 7 -v 8 ) 2350 / 2750 1dh v 29' v 2 +(v 1 -v 2 ) 300 / 2750 v 29'' v 8 +(v 7 -v 8 ) 2450 / 2750 1eh v 30' v 2 +(v 1 -v 2 ) 200 / 2750 v 30'' v 8 +(v 7 -v 8 ) 2550 / 2750 1fh v 31' v 2 +(v 1 -v 2 ) 100 / 2750 v 31'' v 8 +(v 7 -v 8 ) 2650 / 2750 20h v 32' v 2 v 32'' v 7 21h v 33' v 3 +(v 2 -v 3 ) 1500 / 1600 v 33'' v 7 +(v 6 -v 7 ) 100 / 1600 22h v 34' v 3 +(v 2 -v 3 ) 1400 / 1600 v 34'' v 7 +(v 6 -v 7 ) 200 / 1600 23h v 35' v 3 +(v 2 -v 3 ) 1300 / 1600 v 35'' v 7 +(v 6 -v 7 ) 300 / 1600 24h v 36' v 3 +(v 2 -v 3 ) 1200 / 1600 v 36'' v 7 +(v 6 -v 7 ) 400 / 1600 25h v 37' v 3 +(v 2 -v 3 ) 1100 / 1600 v 37'' v 7 +(v 6 -v 7 ) 500 / 1600 26h v 38' v 3 +(v 2 -v 3 ) 1000 / 1600 v 38'' v 7 +(v 6 -v 7 ) 600 / 1600 27h v 39' v 3 +(v 2 -v 3 ) 900 / 1600 v 39'' v 7 +(v 6 -v 7 ) 700 / 1600 28h v 40' v 3 +(v 2 -v 3 ) 800 / 1600 v 40'' v 7 +(v 6 -v 7 ) 800 / 1600 29h v 41' v 3 +(v 2 -v 3 ) 700 / 1600 v 41'' v 7 +(v 6 -v 7 ) 900 / 1600 2ah v 42' v 3 +(v 2 -v 3 ) 600 / 1600 v 42'' v 7 +(v 6 -v 7 ) 1000 / 1600 2bh v 43' v 3 +(v 2 -v 3 ) 500 / 1600 v 43'' v 7 +(v 6 -v 7 ) 1100 / 1600 2ch v 44' v 3 +(v 2 -v 3 ) 400 / 1600 v 44'' v 7 +(v 6 -v 7 ) 1200 / 1600 2dh v 45' v 3 +(v 2 -v 3 ) 300 / 1600 v 45'' v 7 +(v 6 -v 7 ) 1300 / 1600 2eh v 46' v 3 +(v 2 -v 3 ) 200 / 1600 v 46'' v 7 +(v 6 -v 7 ) 1400 / 1600 2fh v 47' v 3 +(v 2 -v 3 ) 100 / 1600 v 47'' v 7 +(v 6 -v 7 ) 1500 / 1600 30h v 48' v 3 v 48'' v 6 31h v 49' v 4 +(v 3 -v 4 ) 3350 / 3450 v 49'' v 6 +(v 5 -v 6 ) 100 / 3450 32h v 50' v 4 +(v 3 -v 4 ) 3250 / 3450 v 50'' v 6 +(v 5 -v 6 ) 200 / 3450 33h v 51' v 4 +(v 3 -v 4 ) 3150 / 3450 v 51'' v 6 +(v 5 -v 6 ) 300 / 3450 34h v 52' v 4 +(v 3 -v 4 ) 3050 / 3450 v 52'' v 6 +(v 5 -v 6 ) 400 / 3450 35h v 53' v 4 +(v 3 -v 4 ) 2950 / 3450 v 53'' v 6 +(v 5 -v 6 ) 500 / 3450 36h v 54' v 4 +(v 3 -v 4 ) 2800 / 3450 v 54'' v 6 +(v 5 -v 6 ) 650 / 3450 37h v 55' v 4 +(v 3 -v 4 ) 2650 / 3450 v 55'' v 6 +(v 5 -v 6 ) 800 / 3450 38h v 56' v 4 +(v 3 -v 4 ) 2500 / 3450 v 56'' v 6 +(v 5 -v 6 ) 950 / 3450 39h v 57' v 4 +(v 3 -v 4 ) 2300 / 3450 v 57'' v 6 +(v 5 -v 6 ) 1150 / 3450 3ah v 58' v 4 +(v 3 -v 4 ) 2100 / 3450 v 58'' v 6 +(v 5 -v 6 ) 1350 / 3450 3bh v 59' v 4 +(v 3 -v 4 ) 1850 / 3450 v 59'' v 6 +(v 5 -v 6 ) 1600 / 3450 3ch v 60' v 4 +(v 3 -v 4 ) 1600 / 3450 v 60'' v 6 +(v 5 -v 6 ) 1850 / 3450 3dh v 61' v 4 +(v 3 -v 4 ) 1300 / 3450 v 61'' v 6 +(v 5 -v 6 ) 2150 / 3450 3eh v 62' v 4 +(v 3 -v 4 ) 800 / 3450 v 62'' v 6 +(v 5 -v 6 ) 2650 / 3450 3fh v 63' v 4 v 63'' v 5 out p ut volta g e 1 out p ut volta g e 2
data sheet s15843ej3v0ds 9 pd160061 6. relationship between input data and output pin data format : 6 bits x 2 rgbs (6 dots) input width : 36 bits (2-pixel data) (1) r,/l = h (right shift) output s 1 s 2 s 3 s 4 ... s 383 s 384 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 ... d 40 to d 45 d 50 to d 55 (2) r,/l = l (left shift) output s 1 s 2 s 3 s 4 ... s 383 s 384 data d 00 to d 05 d 10 to d 15 d 20 to d 25 d 30 to d 35 ... d 40 to d 45 d 50 to d 55 pol s 2n?1 note s 2n note l v 0 to v 4 v 5 to v 9 h v 5 to v 9 v 0 to v 4 note s 2n?1 (odd output), s 2n (even output)
data sheet s15843ej3v0ds 10 pd160061 7. relationship between stb clk and output waveform figure 7?1. input ci rcuit block diagram dac + output amp. sw1 sn (v x ) v amp(in) - figure 7?2. output circuit timing waveform stb s n (v x ) clk v amp(in) hi-z [1] [1'] t stb-clk sw1: off stb = h is loaded with the rising edge of clk[1]. however, when not satisfyi ng the specification of f stb-clk , stb = h is loaded with the rising edge of the next clk[1 ]. latch operation of display data is completed with the falling edge of the next clk which loaded stb = h. therefore, in order to complete latch operation of display data, it is necessary to input at least 2 clk in stb = h period. besides, after loading stb= h to the timing of [1], it is necessary to continue inputting clk.
data sheet s15843ej3v0ds 11 pd160061 8. relationship between stb, pol and output waveform when the stb is high level, all output s became hi-z and the gray-scale voltage is output to the lcd in synchronization with the falling edge of stb. therefore, high drive time of the output amplifier as below is determined by the clk number of the required src pin setting. be sure to avoid using such as extremely changing the clk frequency (ex. clk stop). hi-z stb inside bias current pol vx (odd output) vx (even output) hi-z hi-z v 5 - v 9 v 0 - v 4 v 0 - v 4 v 0 - v 4 v 5 - v 9 v 5 - v 9 high drive time high drive time high drive time 9. src and high drive time the pd160061 can control high drive time of the output amplifier by src pin logic (refer to below figure). src = h or open (high drive time: standard mode): high drive time (pwhp) of the output amplifier is in 64 clk period from falling edge of the stb. src = l (high drive time: long-term mode): high drive time (pwhp) of the output amp lifier is in 128 clk period from falling edge of the stb. stb clk inside bias current pwhp we recommend a thorough simulation of the output amplifier in advance when set the src pin.
data sheet s15843ej3v0ds 12 pd160061 10. bias current co ntrol by lpc and hpc the pd160061 can control the bias current of the output amplifier in high drive period and low drive period. bias current lpc hpc panel load high h l heavy middle l or open l normal l or open h or open low h h or open light we recommend a thorough simulation of the output amplifier in advanc e, when set the lpc and hpc pins. refer to the table below for the example of the combinat ion of setting level and panel load, with driver part supply voltage. example of condition lpc hpc src l or open l example 1 load: r l = 5 k ? , c l = 75 pf driver part supply voltage: v dd2 = 7.5 v bias current mode: middle h or open l or open h or open example 2 load: r l = 5 k ? , c l = 75 pf driver part supply voltage: v dd2 = 9.0 v bias current mode: normal h or open h l example 3 load: r l = 40 k ? , c l = 80 pf driver part supply voltage: v dd2 = 9.0 v bias current mode: high l
data sheet s15843ej3v0ds 13 pd160061 11. electrical specifications absolute maximum ratings (t a = 25 c, v ss1 = v ss2 = 0 v) parameter symbol rating unit logic part supply voltage v dd1 ?0.5 to +4.0 v driver part supply voltage v dd2 ?0.5 to +10.0 v logic part input voltage v i1 ?0.5 to v dd1 + 0.5 v driver part input voltage v i2 ?0.5 to v dd2 + 0.5 v logic part output voltage v o1 ?0.5 to v dd1 + 0.5 v driver part output voltage v o2 ?0.5 to v dd2 + 0.5 v operating ambient temperature t a ?10 to +75 c storage temperature t stg ?55 to +125 c caution product quality may suffer if the absolute m aximum rating is exceeded ev en momentarily for any parameter. that is, the absolute maximum ratings are rated values at which the product is on the verge of suffering physical damage, and therefore the product must be used under conditions that ensure that the absolute maximum ratings are not exceeded. recommended operating range (t a = ?10 to +75 c, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit logic part supply voltage v dd1 2.3 3.6 v driver part supply voltage v dd2 7.5 8.5 9.5 v high-level input voltage v ih 0.7 v dd1 v dd1 v low-level input voltage v il 0 0.3 v dd1 v -corrected voltage v 0 to v 4 7.5 v v dd1 9.5 v 0.5 v dd2 v dd2 ? 0.2 v v 5 to v 9 7.5 v v dd1 < 8.5 v 0.2 0.5 v dd2 ? 0.3 v 8.5 v v dd1 9.5 v 0.2 0.5 v dd2 v driver part output voltage v o 0.2 v dd2 ? 0.2 v 2.3 v v dd1 < 2.7 v 40 mhz clock frequency f clk 2.7 v v dd1 3.6 v 65 mhz
data sheet s15843ej3v0ds 14 pd160061 electrical characteristics (t a = ?10 to +75 c, v dd1 = 2.3 to 3.6 v, v dd2 = 7.5 to 9.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit input leak current i il except lpc, hpc, src 1.0 a lpc, hpc, src 150 a high-level output voltage v oh sthr (sthl), i oh = 0 ma v dd1 ? 0.1 v low-level output voltage v ol sthr (sthl), i ol = 0 ma 0.1 v -corrected resistance r v 0 to v 4 = v 5 to v 9 = 4.0 v, v dd2 = 8.5 v 7.9 15.8 23.7 k ? i voh v dd2 = 8.0 v, v x = 7.0 v, v out = 6.5 v note1 ? 20 a driver output current i vol v dd2 = 8.0 v, v x = 1.0 v, v out = 1.5 v note1 20 a output voltage deviation ? v o 10 20 mv output swing difference deviation ? v p?p t a = 25 c, v dd1 = 3.3 v, v dd2 = 8.5 v, v out = 2.0 v, 4.25 v, 6.5 v 3 15 mv logic part dynamic current consumption note2, 3, 4 i dd1 v dd1 4 12 ma driver part dynamic current consumption note2, 4 i dd22 v dd2 , with no load 3.5 8 ma notes 1. v x refers to the output vo ltage of analog output pins s 1 to s 384 . v out refers to the voltage applied to analog output pins s 1 to s 384 . 2. specified at f stb = 65 khz and f clk = 54 mhz. 3. the typ. values refer to an all black or all white input pattern. the max. value refers to the measured values in the dot checkerboard input pattern. 4. refers to the current consum ption per driver when cascades are connected under the a ssumption of xga single-sided mounting (8 units). switching characteristics (t a = ?10 to +75 c, v dd1 = 2.3 to 3.6 v, v dd2 = 7.5 to 9.5 v, v ss1 = v ss2 = 0 v) parameter symbol condition min. typ. max. unit c l = 15 pf, 2.3 v v dd1 < 2.7 v 20 ns start pulse delay time t plh1 c l = 10 pf, 2.7 v v dd1 3.6 v 10.5 ns c l = 10 pf, 2.3 v v dd1 < 2.7 v 20 ns t plh1 c l = 10 pf, 2.7 v v dd1 3.6 v 10.5 ns t plh2 5 s t plh3 8 s t phl2 5 s driver output delay time t phl3 c l = 75 pf, r l = 5 k ? , lpc = l or open, hpc = h or open, src = h or open 8 s c i1 logic input of exclude sthr (sthl), t a = 25c 10 pf input capacitance c i2 sthr (sthl), t a = 25c 5 pf r ln = 1 k ? , c ln = 15 pf gnd output the measurement point c l1 c l2 c l3 c l4 c l5 r l1 r l2 r l3 r l4 r l5
data sheet s15843ej3v0ds 15 pd160061 timing requirements (t a = ?10 to +75 c, v dd1 = 2.3 to 3.6 v, v ss1 = 0 v, t r = t f = 5.0 ns) parameter symbol condition min. typ. max. unit 2.3 v v dd1 < 2.7 v 25 ns clock pulse width pw clk 2.7 v v dd1 3.6 v 15 ns 2.3 v v dd1 < 2.7 v 6 ns clock pulse high period pw clk(h) 2.7 v v dd1 3.6 v 4 ns 2.3 v v dd1 < 2.7 v 6 ns clock pulse low period pw clk(l) 2.7 v v dd1 3.6 v 4 ns data setup time t setup1 4 ns data hold time t hold1 0 ns start pulse setup time t setup2 4 ns start pulse hold time t hold2 0 ns pol21, pol22 setup time t setup3 4 ns pol21, pol22 hold time t hold3 0 ns stb pulse width pw stb 2 clk last data timing t ldt 2 clk stb-clk time t stb -clk stb clk 9 ns time between stb and start pulse t stb-sth stb sthr(sthl) 2 clk pol-stb time t pol-stb pol or stb ?5 ns stb-pol time t stb-pol stb pol or 6 ns remark unless otherwise specified, t he input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 .
data sheet s15843ej3v0ds 16 pd160061 switching characteristics waveform (r,/l = h) unless otherwise specified, t he input level is defined to be v ih = 0.7 v dd1 , v il = 0.3 v dd1 . pw clk(l) clk pol sn (v x ) stb d n0 to d n5 sthr sthl pw clk(h) t r t setup2 invalid d 1 to d 6 t hold2 1 2 1 2 3 64 65 66 t f v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 v dd1 v ss1 pw clk t stb-clk t stb-sth t setup1 90% 10% t hold1 t plh1 t pol-stb t stb-pol t plh3 t plh2 t phl2 t phl3 hi-z target voltage: 10% t ldt pw stb d 7 to d 12 d 1 to d 6 d 7 to d 12 d 373 to d 378 d 379 to d 384 d 385 to d 390 last data invalid invalid v dd1 v ss1 t setup3 t hold3 pol21, pol22 (1st dr.) (1st dr.) invalid target voltage: 2% + ? + ?
data sheet s15843ej3v0ds 17 pd160061 12. recommended mounting conditions the following conditions must be met for mounting conditions of the pd160061. for more details, refer to the semiconductor device mount manual (http://www.n ecel.com/pkg/en/mount/index.html). please consult with our sales offices in case other m ounting process is used, or in case the mounting is done under different conditions. pd160061n - : tcp (tab package) mounting condition mounting method condition soldering heating tool 300 to 350c, heating for 2 to 3 seconds, pressure 100 g (per solder) thermocompression acf (adhesive conductive film) temporary bonding 70 to 100c, pressure 3 to 8 kg/cm 2 , time 3 to 5 seconds. real bonding 165 to 180c, pressure 25 to 45 kg/cm 2 , time 30 to 40 seconds. (when using the anisotropy conductive film sumizac1003 of sumitomo bakelite, ltd.) caution to find out the detailed c onditions for mounting the acf part, please contact the acf manufacturing company. be sure to avoid using tw o or more mounting methods at a time.
data sheet s15843ej3v0ds 18 pd160061 1 2 3 4 voltage application waveform at input pin waveform distortion due to input noise or a reflected wave may cause malfunction. if the input of the cmos device stays in the area between v il (max) and v ih (min) due to noise, etc., the device may malfunction. take care to prevent chattering noise from entering the device when the input level is fixed, and also in the transition period when the input level passes through the area between v il (max) and v ih (min). handling of unused input pins unconnected cmos device inputs can be cause of malfunction. if an input pin is unconnected, it is possible that an internal input level may be generated due to noise, etc., causing malfunction. cmos devices behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd via a resistor if there is a possibility that it will be an output pin. all handling related to unused pins must be judged separately for each device and according to related specifications governing the device. precaution against esd a strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it when it has occurred. environmental control must be adequate. when it is dry, a humidifier should be used. it is recommended to avoid using insulators that easily build up static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work benches and floors should be grounded. the operator should be grounded using a wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with mounted semiconductor devices. status before initialization power-on does not necessarily define the initial status of a mos device. immediately after the power source is turned on, devices with reset functions have not yet been initialized. hence, power-on does not guarantee output pin levels, i/o settings or contents of registers. a device is not initialized until the reset signal is received. a reset operation must be executed immediately after power-on for devices with reset functions. notes for cmos devices
pd160061 reference documents nec semiconductor device reliability /quality control system (c10983e) quality grades on nec semiconductor devices (c11531e) the information in this document is current as of june, 2004. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec electronics data sheets or data books, etc., for the most up-to-date specifications of nec electronics products. not all products and/or types are available in every country. please check with an nec electronics sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec electronics. nec electronics assumes no responsibility for any errors that may appear in this document. nec electronics does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec electronics products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec electronics or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of a customer's equipment shall be done under the full responsibility of the customer. nec electronics assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec electronics endeavors to enhance the quality, reliability and safety of nec electronics products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec electronics products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment and anti-failure features. nec electronics products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to nec electronics products developed based on a customer- designated "quality assurance program" for a specific application. the recommended applications of an nec electronics product depend on its quality grade, as indicated below. customers must check the quality grade of each nec electronics product before using it in a particular application. the quality grade of nec electronics products is "standard" unless otherwise expressly specified in nec electronics data sheets or data books, etc. if customers wish to use nec electronics products in applications not intended by nec electronics, they must contact an nec electronics sales representative in advance to determine nec electronics' willingness to support a given application. (note) ? ? ? ? ? ? m8e 02. 11-1 (1) (2) "nec electronics" as used in this statement means nec electronics corporation and also includes its majority-owned subsidiaries. "nec electronics products" means any product developed or manufactured by or for nec electronics (as defined above). computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots. transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support). aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. "standard": "special": "specific":

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